Various approaches have been developed to address the problem of inadvertent destruction of data stored in a programmable memory. A number of these approaches are directed to protecting against the destruction of data stored in a programmable memory due to uncontrolled operations or malfunctions occurring in a memory writing unit. A conventional approach to implementing such a memory protection scheme involves deployment of redundant circuit elements, such as redundant decoders or flip-flop circuits, to detect the presence of a spurious memory write command. U.S. Pat. No. 4,897,819 to Takizawa et al. and U.S. Pat. No. 5,119,336 to Itoh, are examples of conventional memory protection approaches that employ such redundant circuit elements.
Microprocessors and programmable memory devices are widely used in medical devices which are implanted in the human body in their intended use. It is well understood in the art that the size and power consumption of such medical devices are two parameters that are severely restricted when designing a device which is to be implanted in the body. Another parameter of paramount important is the integrity of programs and data stored in one or more programmable memories of the implantable medical device.
In most implantable medical device applications, size and power consumption considerations are of primary concern, while memory access speed is of secondary importance. A traditional approach to protecting a programmable memory using redundant write signal testing circuitry, although generally providing for decreased memory access time, typically results in a design having increased power consumption and physical memory size requirements. Such prior art memory protection schemes have limited usefulness in applications in which a reduction in memory circuitry size and power consumption is required or desired, such as in medical device applications.
Various implementations of systems and approaches for protecting a programmable memory device are known in the art, some examples of which may be found in the issued U.S. Patents listed in Table 1 below.
TABLE 1 ______________________________________ U.S. Pat. No. Inventor(s) Issue Date ______________________________________ 4,897,819 Takizawa et al. Jan. 30, 1990 5,119,336 Itoh Jun. 2, 1992 5,341,494 Thayer et al. Aug. 23, 1994 ______________________________________
All patents listed in Table 1 hereinabove are hereby incorporated by reference herein in their respective entireties. As those of ordinary skill in the art will appreciate readily upon reading the Summary of the Invention, the Detailed Description of the Various Embodiments, and the claims set forth below, many of the devices and methods disclosed in the patents of Table 1 may be modified advantageously by using the teachings of the present invention.